The present invention relates generally to an integrated circuit (IC) design, and more particularly to a semiconductor layout structure for electrostatic discharge (ESD) protection circuits.
A gate oxide of a metal-oxide-semiconductor (MOS) transistor of an IC is most susceptible to damage. The gate oxide may be destroyed by being contacted with a voltage only a few volts higher than a supply voltage of the IC. It is understood that a regular supply voltage for an IC is about 5.0, 3.3 volts or even lower. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages can be destructive even though the charge and any resulting current are extremely small. For this reason, it is of critical importance to discharge any static electric charge before it damages the IC.
An ESD protection circuit is typically added to an IC at its bond pads. Such protection circuit must allow normal operation of the IC. It means that the protection circuit is effectively isolated from the normally operating core circuit by blocking a current flow through itself to ground or other pads. In an operating IC, electric power is supplied to a VCC pad, electric ground is supplied to a VSS pad, electronic signals are supplied from outside to some pads, and electronic signals generated by the core circuit of the IC are supplied to other pads for delivery to external circuits or devices. In an isolated, unconnected IC, all pads are considered to be electrically floating, or of indeterminate voltages. In most cases, this means the pads are at ground, or zero voltage.
The ESD can arrive at any pad. This can happen, for example, when a person touches some of the pads on the IC. This is the same static electricity that may be painfully experienced by a person who walks across a carpet on a dry day and then touches a grounded metal object. In an isolated IC, the ESD acts as a brief power supply for one or more pads, while the other pads remain floating, or grounded. Because the other pads are grounded, when ESD acts as a power supply at a randomly selected pad, the protection circuit acts differently than it does when the IC is operating normally. When an ESD event occurs, the protection circuit must quickly become conductive so that the electrostatic charge is dissipated to VSS or ground.
The ESD protection circuit, therefore, has two modes: normal operation mode and ESD mode. When an IC is in the normal operation mode, the ESD protection circuit has no effect to the IC. During the ESD mode, the ESD protection circuit serves its purpose of protecting the IC by conducting an electrostatic charge quickly to VSS or ground before it damages the IC.
As technology in circuit designs continue to grow and lower supply voltages are being used, circuits become more vulnerable to early stages of ESD events. Even voltage slightly higher than the supply voltage can damage the IC and the protection circuit itself. It has been found that parasitic four layer PNPN devices called parasitic silicon controlled rectifier (SCR) can be one of the most effective devices in preventing ESD damage due to its low turn-on impedance, low capacitance, low power dissipation, and high current sinking/sourcing capabilities. By using a NMOS transistor to trigger an SCR, a low triggering voltage ESD protection circuit can be achieved.
The conventional SCR ESD protection circuit may have parasitic capacitance and resistance that may create undesired consequences when the SCR ESD protection circuit is used in a high frequency IC. The shortcomings of the parasitic capacitance and resistance include, for example, noise, signal reflection, and reduced power gain.
It is therefore desired to provide a semiconductor layout structure for a SCR ESD protection circuit with a reduced parasitic capacitance and resistance.